asm(" CPSIE i")与asm(" CPSID i")

SAM4S16

Cortex-M3 Interrupt/Exception Control

Cortex-M3 has NVIC (Nested Vector Interrupt Controller), a kind of peripheral, to support up to 255 interrupts.

Other than that, it also has WIC (Wakeup Interrupt Controller), which similar to NVIC, but it doesn’t need any clock to run. Hence it can be used to detect any interrupt during sleep mode without burning energy (no need to have any clock running on system at all).

Since WIC is only available on rev2 Cortex-M3 (currently only LPC17xx that have it), this post will only discuss the NVIC control.

Configurable Priority vs Unconfigurable Priority Interrupt

On Cortex-M3, the exceptions / interrupts are divided into two categories, based on their priority: configurable and unconfigurable. The unconfigurable priority interrupts have fixed priority, and consist of 3 interrupts:

  1. Reset. Invoked on power on and reset
  2. Non Maskable Interrupt. An external interrupt (activated by external pin) that is unstoppable except by reset.
  3. Hard fault. Any fault that is not handled by other fault handlers (memory management fault, bus fault, usage fault) will activate this interrupt. The interrupt is also activated when the other fault handlers are turned off

Those interrupts / exceptions are the basic interrupts that are expected to be handled by the application (read: MUST be implemented by application). The priority is started at -3 for Reset, -2 for NMI, and -1 for Hard fault.

The rest of 252 interrupts are priority configurable, starting at 0 (the highest priority) until 252 (the lowest priority).

Global Interrupt Enable / Disable

During the initial reset, NVIC is turned off. Therefore, the processor cannot receive any interrupts (except for NMI, Reset interrupt, and hard fault). To turn on the interrupts with configurable priority:

“CPSIE I” is a assembly instruction to enable the priority configurable interrupts. Actually, it’s a shortcut to this longer procedure

To turn off the priority configurable interrupts:

Or, taking the longer non-atomic procedure:

Actually, if it is needed, the hard fault interrupt can be turned off as well (along with the priority configurable interrupts) with this command:

Or, using longer non-atomic procedure

To turn on the hard fault interrupt with the other priority configurable interrupts, use:

Or, using longer non-atomic procedure

Enabling / Disabling Group of Interrupts

Since you have up to 255 interrupts, it’s odd to have just single global interrupt on/off. Hence, ARM created a register to enable/disable group of interrupts, based on their priority, the BASEPRI. If you set the BASEPRI, the interrupts with the same priority level or lower (ie. the priority number is bigger than BASEPRI) will be masked.

Here’s how to set it:

The above code will mask the interrupts with priority 5 or below. To reset/disable the BASEPRI, just replace #5 with #0.

Enabling / Disabling Specific Interrupts

This one is very easy. If you look at the Cortex-M3 technical manual, the only thing that you need to do is to set IRQ X ‘Set Enable Register’ (ISER) or ‘Clear Enable Register’ (ICER). For example, to turn on TIMER0 interrupts (Match0, Match1, Capture0, Capture1) on LPC1766, you can use:

The NVIC_EnableIRQ() is in core_cm3.h file at CMSIS library source code. Don’t forget to include “LPC17xx.h” too, before using these functions from core_cm3.h

中文译版

中文版为网站站主所译,水平有限,如有错漏,望读者不吝指出。

Cortex-M3 中断异常控制

Cortex-M3拥有NVIC(嵌套向量中断控制器),一种外设,可以支持255个中断。

除此之外,它还拥有WIC(唤醒中断控制器),与NVIC相似,但是它不需要时钟来支持它运行。因此它可以用来在休眠模式下检测任何中断,而不需要消耗能量(系统中没有时钟在运行)。

自从WIC仅在rev2 Cortex-M3(目前只有LPC17xx拥有它,译者注:现在应该不只LPC17xx有,这是几年前的文章),这篇文件将只讨论NVIC。

优先级配置vs不可配置的优先级中断

在Cortex-M3中,异常/中断被分为两种,基于它们的优先级:可配置与不可配置。不可配置优先级中断有固定的优先级,包含三种中断:

  1. 复位:上电后或复位时有效
  2. 不可屏蔽中断。一个外部中断(由外部引脚激活),除非复位,否则不可停止。
  3. 硬件错误。任意不可被fault handlers处理的错误(内存管理错误,总线错误,使用错误)会触发此中断。这一中断也会在其余fault handler被关闭时触发。

这些中断/异常是期望由应用程序处理的基本中断(read: MUST be implemented by application)。优先级从-3开始是Reset,-2是NML,-1是Hard fault。

剩下的252个中断的优先级是可以配置的,从0(最高优先级)下到252(最低优化级)。

全局中断使能/失能

在初始复件时,NVIC是关闭的。因此,处理器不能接收任何中断(除NMI,复位中断,还有硬件中断)。为了打开具有可配置优先级的中断:

“CPSIE I”是一条汇编指令来使能可配置优先级的中断。实际上,这是下面长指令的简化:

为了关闭可配置优先级中断:

或是使用更长的非原子步骤:

实际上,如果需要的话,硬件错误中断也可以被关闭(还有可配置优先级中断)使用这条命令:

或者,使用更长的非原子程序:

为了打开硬件错误中断和可配置优先级中断,使用:

或是,使用非原子程序:

使能/失能一组中断

既然你有255个中断,只有全局的开关中断是很奇怪的。因此,ARM创建了一个寄存器来使能/失能一组中断,基于它们的优先级,BASEPRI。如果你置位BASEPRI,具有相同或是更低的优先级的中断将会被屏蔽(比如优先级号大于BASEPRI)

这里介绍了如何来进行置位:

上面的代码屏蔽优先级号大于等于5的中断。

使能/失能指定的中断

这个非常简单。如果你查看Cortex-M3技术手册,你只需要置位IRQ X  ‘Set Enable Register’ (ISER) 或 ‘Clear Enable Register’ (ICER)。比如,为了打开TIMER0中断(Match0, Match1, Capture0, Capture1)在LPC1766,你可以使用:

NVIC_EnableIRQ()在CMSIS library source code中的core_cm3.h中。不要忘记在你使用core_cm3.h中的函数前包含”LPC17xx.h”。

未经允许不得转载:TacuLee » asm(" CPSIE i")与asm(" CPSID i")

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