Scalar processors represent a class of computer processors. A scalar processor processes only one datum at a time, with typical data items being integers or floating point numbers).A scalar processor is classified as a SISD processor (Single Instructions, Single Data) in Flynn’s taxonomy.

In-Order Issue with In-Order Completion

In-Order Issue with Out-of-Order Completion: used in scalar RISC processors to improve the performance of instructions that require multiple cycles.

Out-of-Order Issue with Out-of-Order Completion: To allow out-of-order issue, it is necessary to decouple the decode and execute stages of the pipeline. This is done with a buffer referred to as an instruction window.


Superscalar Instruction Issue and Completion Policies

Out dependency(also called write-write dependency):

I1: R3<-R3 op R5

I2: R4<-R3+1

I3: R3<-R5+1

I4: R7<-R3 op R4

Instruction I2 cannot execute before instruction

antidependency(also called read-write dependency):

I1: R3<-R3 op R5

I2: R4<-R3+1

I3: R3<-R5+1Q

I4: R7<-R3 op R4

Instruction I3 cannot complete execution before instruction I2 begins execution and has fetched its operands. This is so because I3 update register R3, which is a source operand for I2.  The term antidependency is used because the constraint is similar to the of a true data dependency, but reversed: Instead of the first instruction producing a value that the second instruction uses, the second instruction destroys a value that the first instruction uses.

Register Renaming

Register renaming is not Duplication of resources. It can cope with output dependency and antidependency.

In essence, register are allocated dynamically by the processor hardware, and they are associated with the values needed by instructions at various points in time. When a new register value is created(i.e., when an instruction executes that has a register as a destination operand), a new register is allocated for that value. Subsequent instructions that access that value as a source operand in that register must go through a renaming process: the register references in those instructions must be revised to refer to the register containing the needed value. Thus, the same original register reference in several different instructions may refer to different actual registers, if different values are intended.

I1: R3b<-R3a op R5a

I2: R4b<-R3b+1

I3: R3c<-R5a+1

I4: R7b<-R3c op R4b

Three hardware techniques that can be used in a superscalar processor to enhance performance: duplication of resources, out-of-order issue, and renaming.

Branch Prediction

With the advent of RISC machines, the delayed branch strategy was explored.

未经允许不得转载:TacuLee » COA——Superscalar

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