COA——Control Unit Operation

Micro Operation

A single micro-operation generally involves a transfer between registers , a transfer between a register and an external bus, or a simple ALU operation.

The control unit of a processor performs two tasks:(1) It causes the processor to execute micro-operations in the proper sequence, determinded by the program being executed, and (2) it generates the control signals that cause each micro-operation to be executed.

The control signals generated by the control unit cause the opening and closing of logic gates, resulting in the transfer of data to and from registers and the operation of the ALU.

1. Operations(opcodes)

2. Addressing modes

3. Registers

4. I/O module interface

5. Memory module interface

6. Interrupt processing structure

Item 1 through 3 are defined by the instruction set. Items 4 and 5 are typically defined by specifying the system bus. Item 6 is defined partially by the system bus and partially by the type of support the processor offers to the operating system.

Constituent Elements of a Program Execution

The Fetch Cycle

Memory address register(MAR): Is connected to the address lines of the address  lines of system bus. It specifies the address in memory for a read or write operation.

Memory buffer register(MBR):  Is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from memory.

Program counter(PC): Holds the address of the next instruction to be fetched.

Instruction register(IR): Holds the last instruction fetched.

Sequence of Events,Fetch Cycle

t1: MAR<-(PC)

t2: MBR<-Memory

PC<-(PC)+I

t3: IR<-(MBR)

Where I is the instruction length.

Note that the second and third micro-operation both take place during the second time unit. The third micro-operation could have been grouped with the fourth without affecting the fetch operation:

t1: MAR<-(PC)

t2: MBR<-Memory

t3: PC<-(PC)+I

IR<-(MBR)

The groupings of micro-operation must follow two simple rules:

  1. The proper sequence of events must be followed.

  2. Conflicts must be avoided.

The Indirect Cycle

Once an instruction is fetched, the next step is to fetch source operands.

t1: MAR<-(IR(Address))

t2; MBR<-Memory

t3: IR(Address)<-(MBR(Address))

The Interrupt Cycle

At the completion of the execute cycle, a test is made to determine whether any enabled interrupts have occurred.

The nature of this cycle varies greatly from one machine to another. We present a very simple sequence of events.

t1: MBR<-(PC)

t2: MAR<-Save_Address

PC<-Routine_Address

t3: Memory<-(MBR)

In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for return the interrupt. Then the MAR is loaded with the address at which teh contents of the PC are to be saved, and the PC is loaded with the address of the start of the interrupt-processing routine. In any case, once this is done, the final step is to store the MBR, which contains the old value of the PC, into memory.

The Execute Cycle

For a machine with N different opcodes there are N different sequences of micro-operations that can occur.

ISZ X

 

t1: MAR<-(IR(address))

t2: MBR<-Memory

t3: MBR<-(MBR)+1

t4: Memory<-(MBR)

If((MBR) = 0) then (PC<-(PC)+I)

Note also that this micro-operation can be performed during the same time unit during which the updated value in MBR is stored back to memory.

BSA X

 

t1: MAR<-(IR(address))

MBR<-(PC)

t2: PC<-(IR(address))

Memory<-(MBR)

t3: PC<-(PC)+I

Control of the Processor

The basic functional elements of the processor are ALU, Registers, Internal data paths, External data paths, Control unit.

Internal data paths are used to move data between registers and between register and ALU. External data paths link registers to memory and I/O modules, often by means of a system bus. The control unit causes operations to happen within the processor.

All micro-operation fall into one of the following categories:

  • Transfer data from one register to another.
  • Transfer data from a register to an external interface(e.g., system bus).
  • Transfer data from an external interface to a register.
  • Perform an arithmetic or logic operation, using registers for input and output.

All of the micro-operations needs to perform one instruction.

The control unit performs two basic tasks:

Sequencing: The control unit causes the processor to step through a series of micro-operations in the proper sequence, based on the program being executed.

Executing: The control unit causes each micro-operation to be performed.

Control Signals

Block Diagram of the Control Unit

Inputs: Clocks(processor cycle time, clock cycle time), Instruction register, Flags, Control signals from control bus.

Instruction register: The opcode of the current instruction is used to determine which micro-operation to perform during the execute cycle.

Outputs: Control signals within the processor(those that cause data to be moved from one register to another, and those that activate specific ALU functions), Control signals to control bus(control signals to memory, and control signals to I/O modules).

Three types of control signals are used: those that activate an ALU function, those that activate a data path, and those that are signals on the external system bus or other external interface.

PC<-(MBR):

A control signal that control signal on the control bus.

A memory read control signal on the control bus.

A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR.

Control signals to logic that add 1 to the contents of the PC and store the result back to the PC.

Control signals go to three separate destinations:

Data paths: The control unit controls the internal flow of data. For example, on instruction fetch, the contents of the memory buffer register are transferred to the instruction register. For each path to be controlled, there is a gate(indicated by a circle in the figure). A control signal from the control unit temporarily opens the gate to let data pass.

ALU: The control unit controls the operation of the ALU by a set of control signals. These signals activate various logic devices and gates within the ALU.

System bus: The control unit sends control signals out onto the control lines of the system bus(e.g., memory READ).

 

Micro-Operation and Control Signals

Internal Processor Organization

CPU with Internal Bus

Single Bus.[微机原理提到过的单、双总线结构,在这里使用的是单总线。]

When an operation involving two operands is performed, one can be obtained from the internal bus, but the other must be obtained from another source. The AC could be used form this purpose, but this limits the flexibility of the system and would not work with a processor with multiple general-purpose registers.

The ALU is a combinatorial circuit with no internal storage.

An operation to add a value from memory to the AC would have the following steps:

t1: MAR<-(IR(address))

t2: MBR<-Memory

t3: Y<-(MBR)

t4: Z<-(AC)+(Y)

t5: AC<-(Z)

The Intel 8085

Intel 8085 CPU Block Diagram

Incrementer/decrementer address latch: Logic that can add 1 to or subtract 1 from the contents of the stack pointer or program counter. This save time by avoiding the use of the ALU for this purpose.

Intel8085 External Signals

51单片机中各个周期的概念

Machine cycles are defined to be equivalent to bus accesses. Thus, the number of machine cycles for an instruction depends on the number of times the processor must communicate with external devices. For example, if an instruction consists of two 8-bit portions, then two machine cycles are required to fetch the instruction. If that instruction involves a 1-byte memory or I/O operation, then a third machine cycle is required for execution.

Hardware Implementation

 

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